1. Field of the Invention
This invention relates to the field of data processing systems. More particularly, this invention relates to the field of error correcting and error detecting mechanisms within data processing systems.
2. Description of the Prior Art
It is known to provide Error Control Coding (ECC) for use in association with blocks of data. The blocks of data may be stored within a memory, transmitted across a data path or subject to some other action which can result in one or more bit errors within the block of data. The error correcting and/or error detecting codes associated with the block of data may provide a variety of different capabilities for correcting and/or detecting bit errors within the block of data. A simple parity bit may serve to detect a single bit error, but have no capability for correcting a hard bit error. More sophisticated error control codes may be capable of detecting and correcting one or more bit errors within a block of data.
Although the action of error correction and error detection is desirable, there is an additional overhead associated with storing, writing, reading, transmitting etc the error control codes in association with the data block. Furthermore, the processing required to use the error control codes to identify and/or detect the bit errors represents an overhead in terms of the circuitry required and/or additional latency which may be involved in accessing a block of data.